The present invention pertains to the signal communication art and, in particular, to a means for synchronizing with, and demodulating split phase encoded data.
Split phase data encoding schemes are well known in the communication art. Raw digital data, i.e. a data bit stream containing a sequence of logic "ones" and "zeros", often contains low frequency signal components since the data is not constrained to be concentric about its central axis, i.e. the total number of ones does not have to equal the total number of zeros. Thus, transmission and reception apparatus, in order to handle raw data, requires the use of complicated and expensive circuitry having a bandwidth suitable for maintaining low frequency components. Moreover, raw digital data may contain long strings of "ones" or "zeros". A data clock regenerated from the bit stream may drift significantly during this period.
The split phase, or Manchester code was developed to avoid these problems. In such encoding systems, logic levels are represented by transitions in the encoded data. That is, a logic level "1" might be represented by a positive data transition, whereas the logic level "0" would be represented by a negative transition. In operation, the split phase encoded data bit stream is very symmetric about its axis whereby there are few, if any, low frequency components to be carried by the transmission system. The split phase code also insures that there is a signal transition in each bit time period regardless of the particular bit pattern being transmitted.
A problem with split phase encoding schemes is that proper decoding requires the resolution of a phase ambiguity. The encoding process operates by sensing the status of the informaion bit stream at a given clock frequency interval and generating the corresponding positive and negative encoded data stream transition. At the decoder, while it is a simple matter to recover the clock frequency, it is difficult to determine whether the recovered signal is synchronous to the transmitted clock frequency, or a 180.degree. phase angle with respect thereto. Phase sense is critical since a necesssary condition for proper decoding is that the recovered clock signal be synchronized to the clock signal used in encoding. Thus, there has been a need for effective synchronizing circuitry to resolve the decoder phase ambiguity of split phase encoded data.
Of the several approaches for resolving the phase ambiguity in the decoder of split phase encoded data known in the art, all of them require elaborate and costly implementation, resulting in a prohibitive cost. Moreover, due to the large number of components required to implement the known synchronizer circuits, system reliability and accuracy has been a problem.